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EH
2004
IEEE
115views Hardware» more  EH 2004»
15 years 10 months ago
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
Jörg Langeheine, Karlheinz Meier, Johannes Sc...
QOFIS
2000
Springer
15 years 10 months ago
On ACK Filtering on a Slow Reverse Channel
ACK filtering has been proposed as a technique to alleviate the congestion at the input of a slow channel located on the reverse path of a TCP connection. Old ACKs waiting at the ...
Chadi Barakat, Eitan Altman
SIGCOMM
1995
ACM
15 years 9 months ago
Performance Bounds in Communication Networks with Variable-Rate Links
In most network models for quality of service support, the communication links interconnecting the switches and gateways are assumed to have fixed bandwidth and zero error rate. T...
Kam Lee
EUROPAR
2008
Springer
15 years 8 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
WSC
1997
15 years 7 months ago
A Sortation System Model
Automotive manufacturing is a complex task involving several steps of machining and assembly. Typically, larger components of an automobile such as the body, engine etc. are assem...
Arun Jayaraman, Ramu Narayanaswamy, Ali K. Gunal