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» A Case for Buffer Servers
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ICPADS
2006
IEEE
16 years 12 days ago
Destination-Based HoL Blocking Elimination
Congestion management is likely to become a critical issue in interconnection networks, as increasing power consumption and cost concerns will lead to the use of smaller networks....
T. Nachiondo, Jose Flich, José Duato
CODES
2005
IEEE
16 years 5 hour ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
IPPS
2005
IEEE
15 years 12 months ago
Effective Instruction Prefetching via Fetch Prestaging
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
Ayose Falcón, Alex Ramírez, Mateo Va...
MICRO
2003
IEEE
108views Hardware» more  MICRO 2003»
15 years 11 months ago
Reducing Design Complexity of the Load/Store Queue
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
Il Park, Chong-liang Ooi, T. N. Vijaykumar
PASTE
2010
ACM
15 years 11 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago