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ANCS
2005
ACM
15 years 11 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
ICDCS
2007
IEEE
15 years 10 months ago
uSense: A Unified Asymmetric Sensing Coverage Architecture for Wireless Sensor Networks
As a key approach to achieve energy efficiency in sensor networks, sensing coverage has been studied extensively. Researchers have designed many coverage protocols to provide vario...
Yu Gu, Joengmin Hwang, Tian He, David Hung-Chang D...
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
15 years 11 months ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
EUROMICRO
1998
IEEE
15 years 10 months ago
Hardware to Software Migration with Real-Time Thread Integration
This paper introduces thread integration, a new method of providing low-cost concurrency for microcontrollers and microprocessors. This post-pass compiler technology effectively i...
Alexander G. Dean, John Paul Shen
IPPS
1998
IEEE
15 years 10 months ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...