116 search results - page 17 / 24 » Beyond Graphs: A New Synthesis. |
151
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DATE
2009
IEEE
16 years 22 days ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
141
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ASYNC
2001
IEEE
15 years 9 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
178
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ISPD
2009
ACM
16 years 23 days ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
150
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LATIN
2010
Springer
15 years 11 months ago
2010
Springer
In this paper, we consider Steiner forest and its generalizations, prize-collecting Steiner forest and k-Steiner forest, when the vertices of the input graph are points in the Euc...
142
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FPGA
1997
ACM
15 years 10 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...