Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

128

ICCAD
1997
IEEE

108views Hardware» more ICCAD 1997»

Fault simulation of interconnect opens in digital CMOS circuits

15 years 10 months ago

Fault simulation of interconnect opens in digital CMOS circuits

Download www.cs.york.ac.uk

We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can a ect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.

Haluk Konuk

Real-time Traffic

Cient Fault Simulator | Die Surface Voltage | Hardware | ICCAD 1997 | Transistor Charge Equations |

claim paper

Related Content

» Digital Integrated Circuit Testing using Transient Signal Analysis

» An unexpected factor in testing for CMOS opens the die surface

» Incremental Diagnosis of Multiple OpenInterconnects

» Safety Evaluation of NanoFabrics

» A Fault Model and a Test Method for Analog Fuzzy Logic Circuits

» A reduction technique of large scale RCG interconnects in complex frequency domain

» Detection of CMOS Defects under Variable Processing Conditions

» A custom FPGA for the simulation of gene regulatory networks

» Designing logic circuits for probabilistic computation in the presence of noise

Post Info
More Details (n/a)

Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	ICCAD
Authors	Haluk Konuk

Comments (0)