Sciweavers

VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
16 years 7 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
231
Voted
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
16 years 7 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
16 years 7 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
141
Voted
VLSID
2009
IEEE
110views VLSI» more  VLSID 2009»
16 years 7 months ago
Security and Dependability of Embedded Systems: A Computer Architects' Perspective
Jörg Henkel, Roshan G. Ragel, Sri Parameswara...
121
Voted
VLSID
2009
IEEE
148views VLSI» more  VLSID 2009»
16 years 7 months ago
DFX and Productivity
Robert C. Aitken
VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
16 years 7 months ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
143
Voted
VLSID
2009
IEEE
142views VLSI» more  VLSID 2009»
16 years 7 months ago
Floorplanning for Partial Reconfiguration in FPGAs
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
VLSID
2009
IEEE
87views VLSI» more  VLSID 2009»
16 years 7 months ago
Soft Error Rates with Inertial and Logical Masking
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
Fan Wang, Vishwani D. Agrawal
166
Voted
VLSID
2009
IEEE
96views VLSI» more  VLSID 2009»
16 years 7 months ago
Efficient Placement of Compressed Code for Parallel Decompression
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
Xiaoke Qin, Prabhat Mishra
VLSID
2009
IEEE
223views VLSI» more  VLSID 2009»
16 years 7 months ago
Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies
Designing MOS decoupling capacitors (DECAPs) in nanotechnologies provides many challenges due to the existing trade-offs among transient time response behavior, area, and gate lea...
Bardia Bozorgzadeh, Ali Afzali-Kusha